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Advanced Simulation & Signal Integrity Principles for High Performance Digital Designs

See also:
Power Sys. Design
SI Fundamentals
High Perf. Design
EMI and SI
SI Principles
->SI for Digital Designs

A Four Day Seminar

Course Overview:

This is an advanced seminar on the principles of high performance simulations, signal integrity engineering and the design of high performance systems. The seminar includes the presentation of the theory of the simulation of semiconductor models and packages, printed wiring boards, cable and connector electrical performance. The theory and formulations are presented in the context of digital representations of the signals, i.e., in terms of their time domain signal properties of amplitude, clock rate, symmetry and rise/fall times.

Transmission line theory discussions include reflections, signal transmission, bus termination techniques and crosstalk in PC boards and connector elements applicable to digital signals. Advanced topics in transmission line theory are also covered, including analysis crosstalk, AC terminations, capacitive and inductive loading of digital interconnects.

HSPICE and other SPICE dialects and "Method of Moments" field calculations of PWB structures will be used to illustrate "Right by Design" principles for the simulation of high performance digital system design. In the context of SPICE simulations, convergence and integration topics are considered. Integration solution methods such as Gear, Trapezoidal, Euler and Newton-Rapson are discussed. Convergence issues and fixes along with the source of computational errors, the use of error bounds and effect on computation time and accuracy of time step selection are also examined and discussed. HSPICE element usage and syntax of more popular CMOS and Bipolar semiconductors and models are presented. Circuit description modularity and the use of SPICE control features important for creating re-usable models are illustrated with specific examples. Some of the more important control and syntax features discussed include .PARAM, .GLOBAL, .MEASURE, .INCLUDE, and the Model Selector.

A representative set of design based case studies will be used to round out this seminar. Topics for case studies include analysis and simulations of clocking architectures, development of accurate "passive simulation" models to characterize backplanes and multi-load busses, the role of SPICE simulations in the development of wire rules and economical construction recommendations for single sided and differential multi-layered PCBs. Lastly, a specific case study will be developed and discussed on the basis of class choice and input.

Course Objective:

This seminar is designed to address the most important theoretical and simulation issues facing high performance architects, logic designers and signal integrity engineers. The case studies have been carefully chosen to address many of the design choices faced by the participants in every contemporary design. The NESA course instructors have "hands on" experience with these problems, having been responsible for some of the highest performance digital interconnects. Correct use of the principles presented herein has a measurable effect on the execution of "Right by Design" principles, EMI system compliance and time to market.

Who Should Attend:

The following high performance system design engineers have been found to benefit the most from this seminar:

  • Signal integrity and analog engineers who depend on the use of simulation tools for design and validation of high performance designs.
  • Logic designers and architects of SONET, Fibre Channel, advanced Gigabit Ethernet and ATM routers, and Frame Relay switches.
  • EMI compliance and design engineers responsible for the timely compliance of systems platforms to the requirements of FCC Part 15, VCCI of Japan and the CE for the Common European market.

It is recommended that for the most effective application of the theory and principles of this course, seminar participants should have completed undergraduate course requirements in a recognized Electrical Engineering, Computer Design or Physics degree program or possess equivalent industrial design experience.

Course Curriculum:

Day 1 - Signal Integrity and Transmission Line Theory and Practice:

Introduction to High Performance Digital Interconnect & Packaging

  • Course Theme - An Off-chip and Near Chip "Simulated Experience"
  • HSPICE is de-facto semiconductor simulation standard
  • What's the best way - "Right by Design" or Post Layout Validation tools?
    • SPICE vs. Transmission Line SI Validators
    • SPICE Behavioral and IBIS modeling

Transmission Line Theory and Practice in Digital System Design

  • Fundamental Transmission Line Equations
  • Impedance/Time Delay Description of Transmission Lines
  • R-L-C Discrete Components as an Approximation to T-Lines
  • Impedance, Reflection and Transmission Coefficients
    • Analytic formulas for stripline and microstrip impedance
    • Limitations of simple formulas
  • Geometric Based models - An overview of numerical methods of field theory
    • Prediction for capacitance, inductance, impedance, propagation delay
    • Crosstalk between signal traces.
  • Discussion of the effects of material dimensions and homogeneity, dielectric constant, line dimensions in printed wiring board design.
  • Introduction to losses in transmission line & interconnect systems - resistive and AC skin effects


Day 1 - Signal Integrity and Transmission Line Theory and Practice, continued:

Coupling & Crosstalk in PWBs & Transmission Lines - Theory and Practice

  • Near-end/Backward Coupling - Formulation, Signal Features & Properties
  • Far-end/Forward Coupling - Formulation, Signal Features & Properties

Connectors & Packages - Discrete Component Coupling - Theory and Practice

  • Common-Mode Component Coupling
  • Mutual Inductance - Equivalent Transformer Coupling
  • Mutual Capacitance
  • Forward & Backward Coupled Components

Case Study 1 - Semiconductor Package Characterization

  • Physical description of package and transmission line topology
  • Experimental characterization fixture and measurement description
  • Impedance and Transmission measurement results
  • Crosstalk measurements and Simultaneous Switching predictions


Day 2 - Advanced Transmission Line Theory, Robust Simulations and Case Study:

Advanced Transmission Line Topics

  • Review of lumped circuit elements in a transmission line environment,
  • Review of distributed and discrete crosstalk theory & practice.
  • Properties of crosstalk and crosstalk coefficients.
  • Electrical scaling laws for distributed and lumped constant systems
    • Risetime to propagation delay and time constant ratios
    • Theory vs. empirical observations
  • Circuit Descriptions of coupled Transmission Line Theory
    • Per Unit RLC Matrix Representations
    • Circuit element representation - R, G, Self & mutual L & C
    • Weak Coupled Impedance, Reflection and Transmission Coefficients
      • Forward & Backward Traveling Wave Crosstalk Components
  • Theory and analysis of lossy transmission lines
    • High performance transmission line cable lossy line effects
    • On-chip metalization as a transmission line medium

Case Study II - Elementary System and Module Clocking

  • Transmission line impedance, losses and termination strategies (series, parallel AC & resistive)
  • Primary and secondary (module) clock distribution architectures - radial and bussed
  • 40 MHz ABT Clock Distribution Example
    • Semiconductor technology, clock frequency clocking edge signal integrity and waveform fidelity, duty cycle maintenance
  • Skew budget, set-up and hold requirements - Bussed clock example
  • 12.5 MHz Multidrop Clock Distribution Example

Introduction to SPICE - SPICE circuit construction, Operating Point Convergence

  • Overview of SPICE circuit representation & construction
  • Newton-Rapson root finding analysis for DC operating point
  • Transient analysis - Basic Algorithms [Diff. Equations, Finite Solutions]
  • Integration Solution Methods [Gear, Trapezoidal, Euler]
    • Properties of the integration algorithms
    • Sample results (supplied in text)


Day 3 - IC Models and HSPICE Execution, Convergence, Accuracy and Execution:

Introduction to SPICE - Managing the Time Step, Execution Time and Accuracy

  • Convergence Issues and Fixes - What is a Converging Time Step?
  • Using .OPTIONS to assist convergence and execution time
  • Time Step Selection
    • By circuit element time constant
    • By waveform risetime
    • By transmission line propagation delay
    • By user choice
  • Local Error Bounds and their effects on computation stability, accuracy and simulation time

Developing Robust Simulation Files - Component and System Level Viewpoints

  • Features of well structured models - modularity, parameterization, in-line documentation
  • Building structured simulation files and libraries - use of the .LIB, .SUBCKT, .INCLUDE, .MODEL, .MACRO features
  • Validation of SPICE device models from semiconductor manufacturers and passive component suppliers - connectors, cables, semiconductor packaging

Building Simulation Model Modularity and Useful HSPICE features

  • Using the common options - .Param, .Global, .Measure, .Lib, .Include
  • HSPICE Transmission Line U-Model Usage
    • U-Model Validity
  • Level-3 U-Model usage
    • Importing LCR matrices
  • Statistical Simulation (i.e. Worst Case, Monte Carlo)
  • Optimization features and usage

IC models (MOS, BJT, and Diodes) and Overview of Parameters

  • Driver and receiver models - elementary parameters - .Model usage
  • How to get started with a semiconductor model - .DC sweep, .TRAN test circuits
  • What characterizes a driver technology:
    • Driver impedance - on-state, off state, in between
    • Drive current limits - what do they mean?
    • Output topology - totem pole vs "Wire OR" technologies
    • Slew rate control - how it affects I/O operation
  • Different CMOS Level models - why and for what?
  • Replacement of receiver complexity with simple equivalencies
  • I/O oriented semiconductor technologies - Low Voltage CMOS, FutureBus, ECL, PECL, TTL compatible Low voltage CMOS
  • Differential output & common mode/differential mode effects


Day 4 - Case Studies in Signal Integrity SPICE Simulation Engineering:

Case Study III - Passive Simulations to Characterize High Performance Interconnect Impedance and Transmission Properties

  • Multi-load clock net simulation example
  • Bussed Backplane designs
  • Capacitive loading effects on impedance
  • Time Domain reflectometer (TDR) simulation and measurements
  • Fully loaded FutureBus backplane simulation active measurements vs. simulation

Case Study IV - The role of SPICE simulation in the development of wiring rules

  • Bypass capacitors and bulk capacitor effects on memory systems
  • Driver choices by signal integrity based simulation
  • Propagation delay and skew vs. bus loading
  • Overshoot, undershoot and signal fidelity degradation
  • Vendor vs. vendor comparisons


Case Study V - Board construction, differential impedance and crosstalk predictions

  • Properties and characteristics of circuit board materials
  • Economical construction recommendations for multi-layer PCBs
  • Differential impedance PCB constructions - edge and broad-side coupled
  • Crosstalk predictions using modified field modelers and SPICE modeling

Case Study VI - Class specific Case Study - Choice of topic is class dependent, TBD by end of Day 2.



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