A Two Day Seminar
Course Overview:
This seminar will provide a comprehensive educational experience in the
principles of signal integrity engineering and SPICE simulation as they
apply to the design of high performance digital systems' electrical
performance. Discussions include transmission line theory as applied to
digital time domain signals will be covered, including signal reflection
and transmission, bus termination techniques and crosstalk in PC boards and
discrete elements. The seminar will also cover an introduction to crosstalk
theory in transmission lines and coupled discrete elements. Simulation, the
methodology and "how to" of setting up SPICE simulations for high
performance digital systems will be addressed. Also covered are
transmission line theory of impedance, ordinary and differential,
transmission, crosstalk and other effects observed in PWB interconnects in
terms of "classical" logarithmic formulas as well as in terms of
numerical methods of fields such as the Method of Moments.
Course Objective:
To provide state-of-the-art theory, simulation and measurement
techniques of digital system signal integrity engineering as they affect
system design, performance, and manufactured costs. Application of course
materials will result in lower risk designs and manufactured costs of interconnect
and PCB components.
Who Should Attend:
- Engineers designing
and testing high performance digital systems.
- Bus and backplane
architects and designers. Semiconductor packaging and interconnect
characterization and component engineers.
- Fine line and SMT
printed circuit layout, manufacturing and printed circuit board
designers , quality control test engineers and technicians.
Course Curriculum:
Day 1 - Part 1 Principles of Signal
Integrity Engineering:
Review of Transmission Line Theory:
- Lossless
transmission line resistive and non-ideal terminations, lumped
parasitic elements in a transmission line environment, lossy lines.
- Electrical scaling
laws for distributed and lumped constant systems
- theory vs. empirical
observations.
Analysis of crosstalk:
- Analysis of
distributed and discrete crosstalk
- Properties of
crosstalk characterization and crosstalk coefficients
- Scaling laws for
crosstalk.
Review of pertinent semi-conductor theory, technologies and
principles:
- Bi-polar ECL and
CMOS SPICE device models. Emphasis will be on devices designed for bus
driving.
- Bypass and bulk
storage problems in high speed design involving fast edge rate
Bi-polar, Bi-CMOS and CMOS designs.
Day 1 - Part 2: Printed Circuit Impedance and
Propagation Delay Prediction Models
Classical formulas for impedance and propagation
delay. Limitation in the use of these formulas.
Overview of numerical methods of field theory
- Prediction of
capacitance inductance, impedance, propagation delay and crosstalk in
coupled signal traces.
Discussion of the effects of material dimensions and
homogeneity, dielectric constant, line dimensions in printed wiring board
design. Losses in interconnect systems.
Day 2 - Part 1: - Digital System SPICE
Methodology and Simulation Case Studies:
System and Module Clocking and Strobes - Clock
Specification:
- Primary and
secondary (module) clock distribution
- Semiconductor
technology, clock frequency, clocking edges, duty cycle requirements,
waveform fidelity
- Transmission line
impedance, losses and termination strategy - (series, parallel
resistive, AC)
- Skew budget, set-up
and hold requirements, clock phases
Physical Bus Structures - Bus Specifications:
- System bus
structures - point to point vs. multi-drop
- Point to point
busses: single vs. multi-load
- Termination strategy
- series, parallel, distributed multi-drop, incident wave and
reflective terminations.
Developing Robust Simulation Files - Component and System Level:
- Building well
structured models - modularity, parameterization inline documentation
- Building of analog
libraries: - .lib, .subckt, .model, .include features
- Schematic capture of
architecture and interconnects
- Validation of SPICE
device models from semiconductor manufacturers
Case Studies of Digital Clocking, Backplanes and Interconnects:
- Case Study 1 - 40MHz
ABT Clock Distribution Design Example
- Case Study 2 - 12.5
MHz Multi-drop Clock Distribution Design Example
- Original
Multi-drop with Thevenin Pull-up / Pull-down Termination
- Original
Multi-drop Design with Series Termination
- Radial
Distribution Design with Series Termination
- Case Study 3 - The
use of Passive Simulations for Impedance and Transmission Properties
- Simulating
transmission line impedance utilizing a SPICE based TDR simulator
- Estimating
transmission line impedance utilizing capacitive and inductive
loading formulas
- Simulating time
domain transmission (TDT) and crosstalk response in PWBs
- Case Study 4 -
FutureBus Backplane Loading Analysis and Simulation
- Capacitive Loading
Issues
- Time Domain
Reflectometer (TDR) - Measurement vs. Simulation
- Fully Loaded,
Active Backplane - Measurement vs. Simulation
The role of SPICE simulation in the development of "Wiring
Rules"
- Bypass capacitors
and bulk capacitor effects on memory systems
- Driver technology
choices by simulation - propagation time, overshoot, undershoot,
output voltage, risetime effects, vendor vs. vendor comparisons
- Transmission line
impedance and termination effects
- X-Talk calculation
using accurate field calculator and SPICE model developer
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