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About NESA

·         Capabilities

·         Design Experience

·         Sample Client List

·         NESA Engineering Tools


·         Design for Signal Integrity of High Performance Interconnects

o        Electrical Analysis and Design Goals

o        Electrical Analysis and Design Methodology

o        Technology Feasibility Analysis

§         Feasibility Analysis for Technology Assessment Flow Chart

o        Performance Analysis and Modeling

o        Logic, Interconnect & Backplane Concept Design

o        Interconnect Component Characterization

o        Reference Design for Semiconductors  

·         Reference Design for Semiconductors and Interconnects

·         EMI and Regulatory Engineering


·         Engineering Seminars

o        Principles of Power Systems Design and Monitoring for Computer Rooms, Workstations and Office Automation

o        Signal Integrity Fundamentals for Digital Design

o        SPICE Simulation and Signal Integrity Principles for High Performance Digital Designs

o        Electromagnetic Interference and Signal Integrity Principles

o        Signal Integrity Principles for Semiconductor Packaging, Printed Wiring Boards, Connectors and Cabling

o        Advanced Simulation & Signal Integrity Principles for High Performance Digital Designs


·         News Archive


·         Abstracts of Documents Available On-line

o        "A Signal Integrity Revolution in Surface Mount Backplane Connectors and SPICE/S-Parameter Extraction Methodology"

o        "Semiconductor Package Power Integrity Fundamentals"

o        "Case Study Power Integrity Study for Cisco Die, Package, PWB Co-Design"

o        "Case Study High End Package Power, Ground Analysis and Methodology"

o        "DDR-II SDRAM Technology and Design Trends"

o        "Optimized Passive Infiniband Cable Equalizer Designs"

o        "Motorola WarpLink Reference Design Platform"

o        "OC-48/2.5 Gbps Interconnect Engineering Design Rules"

o        "Thoughts & Observations about FR-4 Losses in High Speed Designs"

o        "Signal Integrity & Validation of National's Bus LVDS (BLVDS) Technology in Heavily Loaded Backplanes"

o        "The Technology and Design of Gigabit Interconnects for Network and Communication Systems"

o        "Design of Gigabit Copper Fiber Channel Equalized Cabling"

o        "A Distributed Termination Scheme for GTL+ Backplane Bus Designs"

o        "Specification and Characterization of a Multi-GigaHertz Differential Backplane Connector"

o        "Timing Requirements and Analysis of an SDRAM Main Memory Design Utilizing Dual Inline Memory Modules (DIMM's)"

o        "Development of a New Transmission Line Skin Effect Model for SPICE Evaluations - Simulations and Measurements"

o        "MCM Compute Node Thermal Failure - Design or Test Problem?"

o        "Closing the High Speed Signal Integrity Design Loop - The Design, Simulation, and Characterization of a QuickRing® Backplane System"

o        "Bussed Clock Architectures for High Performance, Robust ATM Design Applications"

o        "Simplifying FutureBus Backplane Impedance Predictions and Simulating FutureBus Performance"

o        "Infiniband and the limits of FR-4"

o        "Signal Integrity Solutions for a High Speed GTLP Backplane"

o        "A Baker's Dozen of High-Speed Differential Backplane Design Tips"

·         Publications not available on-line

o        "LVDS: power-miser angel, interconnect demon"

o        "Fast backplane connectors disguise digital transmission lines"



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