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About NESA
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Capabilities
·
Design
Experience
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Sample
Client List
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NESA
Engineering Tools
Services
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Design for
Signal Integrity of High Performance Interconnects
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Electrical
Analysis and Design Goals
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Electrical
Analysis and Design Methodology
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Technology
Feasibility Analysis
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Feasibility
Analysis for Technology Assessment Flow Chart
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Performance
Analysis and Modeling
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Logic,
Interconnect & Backplane Concept Design
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Interconnect
Component Characterization
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Reference
Design for Semiconductors
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Reference
Design for Semiconductors and Interconnects
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EMI and
Regulatory Engineering
Seminars
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Engineering
Seminars
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Principles
of Power Systems Design and Monitoring for Computer Rooms, Workstations and
Office Automation
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Signal
Integrity Fundamentals for Digital Design
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SPICE
Simulation and Signal Integrity Principles for High Performance Digital
Designs
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Electromagnetic
Interference and Signal Integrity Principles
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Signal
Integrity Principles for Semiconductor Packaging, Printed Wiring Boards,
Connectors and Cabling
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Advanced
Simulation & Signal Integrity Principles for High Performance Digital
Designs
News
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News
Archive
Publications
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Abstracts
of Documents Available On-line
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"A
Signal Integrity Revolution in Surface Mount Backplane Connectors and
SPICE/S-Parameter Extraction Methodology"
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"Semiconductor
Package Power Integrity Fundamentals"
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"Case
Study Power Integrity Study for Cisco Die, Package, PWB Co-Design"
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"Case
Study High End Package Power, Ground Analysis and Methodology"
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"DDR-II
SDRAM Technology and Design Trends"
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"Optimized
Passive Infiniband Cable Equalizer Designs"
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"Motorola
WarpLink Reference Design Platform"
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"OC-48/2.5
Gbps Interconnect Engineering Design Rules"
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"Thoughts
& Observations about FR-4 Losses in High Speed Designs"
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"Signal
Integrity & Validation of National's Bus LVDS (BLVDS) Technology in
Heavily Loaded Backplanes"
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"The
Technology and Design of Gigabit Interconnects for Network and
Communication Systems"
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"Design of
Gigabit Copper Fiber Channel Equalized Cabling"
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"A
Distributed Termination Scheme for GTL+ Backplane Bus Designs"
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"Specification
and Characterization of a Multi-GigaHertz Differential Backplane
Connector"
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"Timing
Requirements and Analysis of an SDRAM Main Memory Design Utilizing Dual
Inline Memory Modules (DIMM's)"
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"Development
of a New Transmission Line Skin Effect Model for SPICE Evaluations -
Simulations and Measurements"
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"MCM
Compute Node Thermal Failure - Design or Test Problem?"
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"Closing
the High Speed Signal Integrity Design Loop - The Design, Simulation, and
Characterization of a QuickRing® Backplane System"
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"Bussed
Clock Architectures for High Performance, Robust ATM Design
Applications"
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"Simplifying
FutureBus Backplane Impedance Predictions and Simulating FutureBus
Performance"
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"Infiniband
and the limits of FR-4"
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"Signal
Integrity Solutions for a High Speed GTLP Backplane"
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"A
Baker's Dozen of High-Speed Differential Backplane Design Tips"
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Publications
not available on-line
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"LVDS:
power-miser angel, interconnect demon"
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"Fast
backplane connectors disguise digital transmission lines"
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Send E-Mail
to info@nesa.com
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