This presentation will present some of the developmental results of a
candidate Future I/O (FIO) connector system developed by Fujitsu Takamisawa
Components Limited in Japan and their sister company Fujitsu Takamisawa of
The talk will focus on the validation of the FIO "Passive
Backplane, Option 2" cable interface requirements and what they mean
to system I/O designers and chip manufacturers.
Results will be shown showing the correlation of SPICE simulation
modeling results to equivalent characterization measurement data. The
creation and validation of FIO "Passive Backplane, Option 2"
cable and connector SPICE models is an important step for system designers.
These validated SPICE permit the performance of the FIO interconnects to be
simulated and performance analyzed using realistic Gigabit device driver
and receiver models communicating at Gigabit rates over the FIO connectors
and PCB interconnects.
This presentation will summarize only a small fraction of the work being
pushed forward to create bandwidth at affordable prices and predictable
performance. With the standardization of the System I/O technology, the
previously difficult arena of Gigabit I/O interconnect design will be
replaced by the next millennium System I/O "plug and play"
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