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"Case Study High End Package Power, Ground Analysis and Methodology"

See also:
Surface Mount Backplane Connector...
Semiconductor Package Power...
Case Study of Cisco Package Redesign...
->Case Study of Package Power...
DDR-II SDRAM Technology...
Infiniband Cable Equalizer...
Motorola WarpLink Reference Design...
OC-48/2.5 Gbps Design Rules...
The limits of FR-4...
SI & Validation of BLVDS...
Gigabit Interconnects...
Design of Gigabit Copper Fibre Channel...
GTL+ Backplane Termination...
GHz Differential Connector ...
Timing of SDRAM Design...
Transmission Line Skin Effects...
MCM Compute Node Thermal Failure...
QuickRing Backplane System
Bussed Clock Architectures for ATM...
Simplifying FutureBus Backplane...
Infiniband and the limits...
SI Solutions for GTLP...
A Baker's Dozen...

 

Presented at DesignCon Santa Clara, CA - February 2004

Dr. Edward P. Sayre, P.E.
Dr. Edward P. Sayre, III
Mr. Michael Baxter

Abstract

This Case Study Addresses the Following:

  • Investigate the package of a high performance 64-bit processor chip with autonomous I/Os for power/ground noise generation.
  • The methodology is HSPICE circuit simulation based. HSPICE is the simulator of choice for this analysis due to its flexibility and compatibility with transistor and IBIS I/O and core models descriptions.
  • The chip core characteristics and I/O HSPICE models and general system parameters were provided by the semiconductor client.
  • The high-end processor chip model included the chip core and autonomous I/O transceivers, drivers and receivers. Autonomous I/Os included 264 bits of SSTL memory bus, 266 bits of 100 Mbps GTLP and 60 bits of 66 MHz PCI.

->This paper is available from NESA for $15.00 to cover management costs. We accept credit card payment for purchase of the papers. The requested paper will be emailed to you shortly after your order is received.

 

 

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