at DesignCon Santa Clara,
CA - February 2004
Dr. Edward P. Sayre, P.E.
Dr. Edward P. Sayre, III
Mr. Michael Baxter
This Case Study Addresses the Following:
- Investigate the
package of a high performance 64-bit processor chip with autonomous
I/O’s for power/ground noise generation.
- The methodology is
HSPICE circuit simulation based. HSPICE is the simulator of choice for
this analysis due to its flexibility and compatibility with transistor
and IBIS I/O and core models descriptions.
- The chip core
characteristics and I/O HSPICE models and general system parameters
were provided by the semiconductor client.
- The high-end
processor chip model included the chip core and autonomous I/O
transceivers, drivers and receivers. Autonomous I/O’s included 264
bits of SSTL memory bus, 266 bits of 100 Mbps GTLP and 60 bits of 66
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