"Timing Requirements and Analysis of an SDRAM Main Memory Design Utilizing Dual Inline Memory Modules (DIMM's)"

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Presented at the Design Supercon97 Dr. Edward P. Sayre, P.E. Dr. Jinhua Chen Edward P. Sayre, III, M.S.E.E Abstract This paper develops the timing requirements for the use of Dual Inline Memory Module (DIMM) Synchronous Dynamic Random Access Memory (SDRAMs) .as main memory elements in high end PC and other memory systems. The memory must work over the range of 66 and 83 Mhz. The study and design also determined the limits to 100 MHz operation. The analysis proceeds with the development of a timing spreadsheet which takes into account worst case chip, connector PCB trace and main clocking skews. A method was developed to determine optimum timing margins based on the spread sheet, SPICE simulation of the address and data paths and static timing analyzer results. ->This paper is available from NESA for $15.00 to cover management costs. We accept credit card payment for purchase of the papers. The requested paper will be emailed to you shortly after your order is received.

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