in the Design Supercon95 Proceedings
Mr. Hansel A. Collins, B.S.E.E.
Dr. Edward P. Sayre, P.E.
ATM backbone systems designed for communication
applications require such features as: high performance logic and
interconnects with the ability to support a wide variety of system
configurations, high availability and reliability achieved with hot swap
redundant logic and power supplies. In such systems, the wide variations in
logic card configurations are dictated by the market and customer needs and
affect clocking and interconnect performance. In such systems, the
"coincident" clock distribution schemes found in high-end
computer systems are impractical due to their highly restrictive
configuration rules. For high performance ATM based communication systems,
up to and beyond 50 MHz, a "non-coincident" multi-drop
distribution clocking scheme, also known as a "bussed clock",
offers a low cost alternative without the restrictive configuration rules
of the traditional clock distribution networks. The advantages of a bussed
clock design include resistance to differences in clock driver delay and
insensitivity to unbalanced module configurations. But these formidable
advantages can be offset if the signal integrity and timing issues addressed
in this paper are not taken into account.
Since the timing on a bussed clock is sensitive to the relative location
of the data drivers and receivers, all aspects of the clock network and
timing must be well defined. The following are some of the issues to be
addressed in ATM switch backbone designs:
- The importance of
designing the receiving modules' clock circuits to be electrically
- Designing for
incident wave switching of the backplane clocks for the highest
- Routing issues and
pinning out of connectors to give clocks the best signal integrity;
- The use of SPICE
simulation to verify signal integrity and obtain delay information to
feed into the timing analysis for confirmation of proper bus
- Timing analysis
which takes into account differences in module bus loading and card
These and other issues will be discussed in detail with design examples
presented to clearly demonstrate important topics.
This paper extends past work by North East Systems Associates, Inc. in
the design of FutureBus+ based designs for ATM applications. In earlier
work,  the theoretical
justification for the application of the backplane capacitive loading
formulas in determining impedance and propagation delay was established. These
results were correlated to the more exact mixed transmission line and
discrete component SPICE simulated backplane model results and
This established methodology is used in the determination of the loaded
backplane timing models. FutureBus+ technology has been chosen as an
example case to illustrate the validity of the analysis methodology
for"bussed" high performance clocking.
 "FutureBus+ Backplane Impedance Prediction and
Performance", Michael A. Baxter and Dr. Edward P. Sayre, interConnection
Technology, October, 1992.
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